Danville Signal Processing dspstak 21262sx User Manual

Danville Signal Processing, Inc. dspstak™ 21262sx User Manual Version 1.00

JTAG Emulation Port The dspstak 21262sx has a right angle JTAG connector (JH3) mounted on the lower edge of the pcb assembly. This connector is asses

Module, then you may map the DAI any way you want on the Interconnect Port. We expect that future dspstak DSP Engines will also have DAI mapped connec

Row A&C B Name Notes 20 * RFS0 DAI 7 20 * TFS0 DAI 8 21 * RCLK0 DAI 9 21 * TCLK0 DAI 10 22 * #RESET0 PLD 22 * G

Parallel Port The Parallel Port is connected to two major components, the USB Port and a PLD that is used to create and manage much of the dspstak’s

SPI Port The SPI is used as a general purpose control bus on the dspstak 21262sx. It is connected to two onboard components, a serial flash memory an

Programming the dspstak™ 21262sx The dspstak 21262sx can be programmed in a variety of ways. In most cases, programs are uploaded via either the USB

Configuration Jumpers JH5 is also used to select the boot configuration and clock configuration of the ADSP-21262. The connections are made directly

Clock reprogramming is managed entirely by the Peripheral Microcontroller via its RS-232 port. It is not dependent on the ADSP-21262 DSP. The Periphe

Uploading Programs – Mode 6 The dspstak 21262sx uses a 2Mbit SPI serial flash memory device to bootload the ADSP-21262. Assuming that the boot mode s

Here are the basic steps to uploading programs: • Configure the dspstak 21262sx to operate in Mode 6. • Connect to an ASCII Terminal Program via R

Danville Signal Processing, Inc. dspstak™ 21262sx User Manual Copyright © 2004 Danville Signal Processing, Inc. All rights reserved. Printed in the

• After the program is uploaded, a checksum is calculated and you have the opportunity to enter a description of the program. The program description

Peripheral Microcontroller API The Peripheral Microcontroller communicates via the SPI bus using a 3 byte packet structure. Flag 1 serves as the SPI

System Commands Status Description: Peripheral Microcontroller Status Command: Any Status is automatically updated each time a packet is transmi

PM_Cmd_VERSION Description: Returns the firmware version of the Peripheral Microcontroller Command: 0x03 Data: Don’t Care Response: 0x00 The cur

PM_Cmd_RESET Description: Reset the dspstak 21262sx Command: 0x0A Data: 0xC4 Response: Don’t Care This is a software reset that acts just like a

PM_Cmd_RESYNC Description: Resync the Peripheral Microcontroller Command: 0x0F Data: 0x0F Byte 3 (DSP): 0x0F Response: 0x00 This command is use

PM_Cmd_COM_BAUD Description: Sets the Baud rate Command: 0x04 Data: See Below Response: 0x00 Baud = (1.152 * 10^6 ) / (DATA + 1) Typical Value

PM_Cmd_EE_WREN Description: Enables Writes to the EE Memory Command: 0x09 Data: 0x42 (Enable), All other values (Disable) Response: 0x00 This

USB & PLD Registers The dspstak 21262sx uses a PLD for I/O expansion. It is connected to the DSP’s Parallel Port. The USB port is also connected

Memory Map Name Addr Dir Bits Used Description USB_DATA 0x8000 R/W D7-D0 USB Data Bus USB_STATUS 0x9000 R D15-D12 USB Status PLD_D

Table of Contents Overview ...5 Introducing dspstak™...

USB Status Bits Address: 0x9000 PWREN: D14 0 – USB Port is enumerated TXE: D13 0 – Transmit FIFO can accept a byte RXF: D12 0 – Rec

PLD Output Registers PLD_DAI_SPI_SELECT Description: Selects I/O or SPI SS mapping Destination: Interconnect Port Address: 0xA000 IO7/#SPISS3

PLD_OUT1 Description: 3.3V Digital Output Destination: Interconnect Port Address: 0xC000 #RESET: D15 0 – Output Low #RESET1 D14

PLD_WD Description: 3.3V Digital Output Destination: Peripheral Microcontroller Address: 0xE000 All data bits are Don’t Care. A write to

dspstak™ 21262sx User Manual Page 34 Product Warranty Danville Signal Processing, Inc. products carry the following warranty: Danville Signal

USB & PLD Registers...28 Addressing USB & PLD Registers...

Overview DSP-based embedded applications often take the form of a digital signal processing engine coupled with a specialized data conversion and si

Intended Audience The dspstak 21262sx is intended for DSP systems integrators, designers and programmers who may wish to integrate a dspstak into the

• Analog Devices ADSP-2126x SHARC® DSP Peripherals Manual • Analog Devices ADSP-21262S Product Data Sheet • Cypress Semiconductor CyberClocks™ Our

Volt Digital) and Vd+3.3 (3.3V Digital) are created and made available to the I/O Modules via the Interconnect Port. The DSP Core voltage, Vd+1.2 is a

When the dspstak 21262sx is programmed using the RS-232 interface, only RD & TD are used. DTR, DSR & DCD are simply connected together and ign